1. Field of the Invention
The present invention relates to integrated circuit processing and in particular to photo lithography and patterning of semiconductor wafers. More specifically, the present invention is directed to processing of very large area integrated circuits such as infrared focal plane array readout circuits, charge coupled devices, and other imaging devices, random access memories, sequentially accessed memories, and other large area integrated circuit devices having repeating features in the integrated circuit pattern.
2. Description of the Prior Art and Related Information
During processing of semiconductor devices the semiconductor wafer must be exposed with the integrated circuit pattern for each integrated circuit on the wafer for each processing layer. Typically, the entire circuit pattern on the appropriate substrate for an integrated circuit device (or at least for a given layer of the device) is provided by repeatedly stepping and exposing a single image reticle or by a mask that has all copies of the circuit pattern which are transferred in a single exposure.
Reticle based exposure equipment, where the integrated circuit pattern is exposed repeatedly across the entire wafer, is suitable for integrated circuits requiring high density line and spacing features below approximately one micron and having dimensions of about 18 mm to 22 mm on a side or less. These size dimensions correspond to the maximum exposure image for currently available wafer stepper lens which typically have an image magnification reduction of 5 times. In many applications, integrated circuits larger than 18 to 22 mm on a side are highly desirable. For example, high resolution imaging devices with large numbers of pixels, e.g., 1024 by 1024 and greater, generally require such larger area integrated circuits.
For patterning larger area integrated circuits, i.e., those greater than 18-22 mm on a side, older technology 1.times. projection aligners that can pattern an entire semiconductor wafer with a single image are typically employed. However, the smallest feature size that can currently be patterned by such projection aligners is typically above 1.5 microns which limits the achievable circuit functionality. While such coarse pattern resolution is generally acceptable for certain large area integrated circuits, such as some charge coupled devices (CCDs) and low density infrared focal plane array readout integrated circuits (ROICs), such feature resolution is generally not adequate for many other applications. For example, memory chips, high resolution CCDS, focal plane array ROICs having small detector pitches (less than 25 microns) or focal plane array ROICs with large numbers of active devices for each input are generally not suitable for fabrication using 1.times. projection aligners.
Accordingly, a need presently exists for a method for patterning very large area integrated circuits with a pattern resolution or design rule feature much better than 1.5 microns.